UIT

ASIC LAB

The Hub of IC Design Excellence at UIT.

ASIC LAB UIT is a specialized research unit focused on the entire lifecycle of **Application-Specific Integrated Circuits** — from architectural definition to physical implementation.

We empower students and researchers to master industry-standard EDA tools, bridging the gap between academic theory and Silicon reality.

ASICCore

Design to Silicon

SoC • VLSI • FPGA

Vision

To become a leading organization in education and research, building a sustainable global knowledge community.

Mission

To provide high-quality educational solutions and drive applied research for professional growth and community development.

Quality

Premium Service Standards

Innovation

Tech-Driven Solutions

Collaboration

Growing Stronger Together

Responsibility

Commitment to Society

Research Directions

SoC Design

Design and development of integrated systems on a single chip.

Embedded IoT

Development of embedded systems for IoT and smart networks.

ASIC Design

Custom IC design from RTL to physical implementation.

VLSI System

Large-Scale Integration focusing on layout and simulation.

FPGA & Digital

Digital system design and FPGA prototyping for architectures.

Our Service

Short Courses

Intensive professional training programs focusing on IC Design, AIoT, and semiconductor technologies with industry-standard curriculum.

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Equipments

Provision of cutting-edge industrial measurement tools, development boards, and testing systems with comprehensive technical support.

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Internships

Hands-on career development opportunities for students to work on real-world projects alongside experienced semiconductor experts.

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Supporting Activities

Education & Training

Professional training
Scientific workshops
Scholarship programs

Community & Collaboration

Networking
Volunteering activities
Leadership development

International Partnerships

Academic exchange
Joint projects
Exchange programs

Lab Moments

IC PHYSICAL DESIGN FUNDAMENTALS

KHÓA ĐÀO TẠO “IC PHYSICAL DESIGN FUNDAMENTALS” DÀNH CHO BẠN! Phòng thí nghiệm Nghiên cứu Thiết kế vi mạch tích hợp chuyên dụng (ASICLAB) trực thuộc Trường Đại học Công nghệ Thông tin - Đại học Quốc gia TP.HCM phối hợp với Tập đoàn Cadence số một thế giới về thiết kế chip hân hạnh thông báo về việc khai giảng khóa đào tạo "Thiết kế Vật lý Vi mạch Nền tảng". Sự hợp tác này tài trợ nhiều suất học bổng đến 100% học phí cho khóa học, và hỗ trợ kết nối việc làm sau khi hoàn thành khóa học. Một thiết kế dù tốt đến đâu trên lý thuyết cũng không thể sản xuất nếu thiếu đi bàn tay của kỹ sư Physical Design (PD) để đưa nó lên mặt silicon một cách tối ưu và không có lỗi vật lý. Khóa học này sẽ đào tạo bạn từ những khái niệm cốt lõi đến quy trình triển khai thực tế—một trong những vị trí có nhu cầu tuyển dụng "khát" nhân lực nhất ngành bán dẫn hiện nay.

Summary of the ASIC Lab Academic Seminar 2025

On October 15, 2025, at the University of Information Technology – VNU-HCM, ASIC LAB, in collaboration with SHTP-IC, successfully organized the second Academic Seminar of 2025. The seminar focused on integrated circuit (IC) testing and post-fabrication high-speed IP interface measurement and validation processes, attracting significant interest from lecturers, students, researchers, and engineers.

A delegation from Coherent Vietnam visited

On the afternoon of September 24, a delegation from Coherent Vietnam paid a visit and held a working session at the Application-Specific Integrated Circuits Laboratory (ASIC Lab) of the University of Information Technology, VNU-HCM, opening up promising opportunities for collaboration in semiconductor education and research.

DVClub Vietnam | High Performance Computing & Automotive 2025

In the context of the rapid growth of AI, high-performance computing (HPC), and autonomous vehicles, the challenges of verification, performance optimization, and ensuring safety and security for increasingly complex SoC architectures have become critical. DVClub Vietnam 2025 is organized to provide an in-depth forum for technical exchange, foster academia–industry collaboration, and update participants on next-generation verification trends.